Impact of Cache Coherence Protocols on the Power Consumption of STT-RAM-Based LLC

To gain higher density and lower leakage, STT-RAM has been considered an alternative to SRAM for implementing last-level caches (LLCs). However, STT-RAM requires high write energy to program. Consequently, frequent write-backs from the upper-level caches or cache fills from the main memory will result in high LLC power. Both the broadcast and write-back traffic are affected by the cache coherence protocol. In this paper, we study the impact of coherence protocols on the power consumption of the STT-RAM LLC, and the entire cache hierarchy (including the interconnection power). Based on full-system simulation executing multi-threaded benchmarks, we show that although for some of the workloads, different protocols produce very different broadcast or write-back traffic, for these workloads, the interconnection and the write-back power are only a small fraction of the overall power consumption. Cache coherence protocol thus has very little impact on the power of the STT-RAM LLC and the cache hierarchy.